The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a cellular application 50 requires accurate clock references for receivers associated with a cellular transceiver module 52 and a global positioning system (GPS) receiver module 54. The cellular transceiver module 52 receives a first clock reference ClkInXCVR from a voltage controlled, temperature compensated crystal oscillator (VC-TCXO) clock module 60.
The cellular transceiver module 52 receives RF signals including reference tones or other signals bearing timing information via one or more antennas 53. The RF signals are downconverted to baseband. A baseband module 68 receives the downconverted signals and generates digital automatic frequency control (AFC) signals. The cellular transceiver module 52 includes a DAC 66 that converts the digital AFC signals to analog AFC signals for output to the VC-TCXO clock module 60. The VC-TCXO clock module 60 corrects the first clock reference ClkInXCVR based on the analog AFC signals. The clock reference ClkInXCVR is adjusted to compensate for Doppler, temperature, and other effects.
However, the GPS receiver module 54 cannot use the first clock reference since it cannot tolerate abrupt frequency changes that occur in the first clock reference ClkInXCVR from the VC-TCXO clock module 60 during AFC correction. As a result, an additional TCXO clock module 58 is typically used to generate a second clock reference ClkInGPS for the GPS receiver module 54. The second clock reference is not AFC-corrected. The TCXO clock module 58 is implemented in addition to the AFC-corrected VC-TCXO clock module 60 used for the cellular transceiver module 52.
Referring now to FIG. 2, a cellular application 75 includes a first clock module 77 that provides a first clock reference to a GPS receiver module 79. A second clock module 82 provides a second clock reference to a clock distribution module 80 of a cellular transceiver module 81. The clock distribution module 80 may include a buffer 84 to buffer the second clock reference before the second clock reference is received by an internal clock distribution module 86.
A receiver phase lock loop (RxPLL) module 94 receives the second clock reference from the clock distribution module 80. The RxPLL module 94 includes a phase frequency detector (PFD) 96 that detects a phase difference between the second clock reference and a third clock reference output by a divider 104. The PFD 96 outputs the phase difference to a charge pump 98. An output of the charge pump 98 is filtered by a low pass filter (LPF) 100 and then output to a voltage controlled oscillator (VCO) 102. The VCO 102 outputs a fourth clock reference to the divider 104, which divides the fourth clock reference by a value selected from a set of one or more integer values to generate the third clock reference.
A receiver module 109 includes a low noise amplifier (LNA) 110 that receives and amplifies a radio frequency (RF) input. A downconverter 112 downconverts the RF input signal to a baseband signal. A combination filter and programmable gain amplifier (PGA) 118 filters and amplifies the baseband signal.
A combination analog to digital converter (ADC) and digital signal processor (DSP) module 124 includes an ADC module 128 and a receiver DSP 130. The ADC module 128 converts the baseband signal, as filtered and amplified, to a digital baseband signal. The receiver DSP 130 performs digital signal processing on the digital baseband signal.
An output of the receiver DSP 130 is received by a digital interface module 134, which provides an interface between a baseband module 135 and the cellular transceiver module 81. The baseband module 135 performs baseband processing on the digital baseband signal. The baseband module 135 also receives a system clock (SYSCLOCK) from the internal clock distribution module 86 via a buffer 136.
The baseband module 135 includes an automatic frequency correction (AFC) module 137 that processed the digital baseband signal to recover frequency error of the second clock reference. The AFC module 137 generates a digital AFC signal to correct the frequency error. The digital AFC signal is output via the digital interface module 134 to a digital to analog converter (DAC) 140. The DAC 140 generates an analog AFC signal, which is output to the second clock module 82. The second clock module 82 corrects the second clock reference based on the analog AFC signal.
The adjustments made in response to the analog AFC signal may cause abrupt frequency or phase changes in the second clock reference. While the abrupt clock reference changes may be acceptable to the cellular transceiver module 81, the changes are not acceptable to the GPS receiver module 79. As a result, both the first clock module 77 and the second clock module 82 is implemented.